Device isolation process flow for ARS system

ABSTRACT

A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.

TECHNICAL FIELD

[0001] The technical field relates to an atomic resolution storage (ARS)system, and, in particular, to device isolation process flow for the ARSsystem.

BACKGROUND

[0002] An ARS system provides a thumbnail-size device with storagedensities greater than one terabit (1,000 gigabits) per square inch. TheARS technology builds on advances in atomic probe microscopy, in which aprobe field emitter tip as small as a single atom scans the surface of amaterial to produce images accurate within a few nanometers. Probestorage technology may employ an array of atom-size probe field emittertips to read and write data to spots on storage media.

[0003] An ARS system typically includes three bonded silicon (Si)wafers, i.e., a tip wafer, also known as an emitter wafer, a rotorwafer, also known as a mover wafer, and a stator wafer. The wafers arebonded together using wafer bonding techniques, which are well known inthe art.

[0004]FIG. 1 illustrates a prior art ARS system, where all diodes sharecommon electrodes. A tip wafer 110 includes a plurality of field emittertips 114. A phase change layer 123, which may serve as a storage mediato store data bits, is deposited on a substrate rotor wafer 120, alsoknown as mover wafer. The substrate rotor wafer 120 is a highly doped Sisubstrate, which may be a n-type substrate or a p-type substrate. Acapping layer 160 is coated over the phase change layer 123 to protectthe phase change layer 123 and to prevent evaporation of material whenheat is applied. The capping layer 160 also modifies the surface statesof the phase change layer 123. Electron beam focusing electrodes 113enables focused electron bean 116 to change the phase of media filmlocally. The rotor wafer 120 may move in x and y direction, as shown inFIG. 1, to allow data bits to be written to or read from the storagemedia.

[0005] The ARS storage media uses p-n junction diodes, i.e., devicesembedded in a top active Si layer for reading the data bit. In the priorart ARS system, the diodes share common electrodes (not shown), whichmay increase cross talk between devices, leading to higher electricalnoise.

SUMMARY

[0006] A method for device isolation for an ARS system includes formingan insulating layer between a wafer substrate, such as a rotor wafer,and a top active Si layer, forming a phase change layer over the topactive Si layer, depositing, patterning, and selectively etching amasking layer over the phase change layer, and etching the top active Silayer using the masking layer as a mask until reaching the insulatinglayer. As a result, diodes, i.e., devices embedded in the top active Silayer, may become electrically isolated from one another to enhancesignal to noise ratio for the ARS system.

[0007] In an embodiment of the device isolation process flow, theinsulating layer is formed by ion implantation of oxygen beneath the topactive Si layer on the wafer substrate and heating the oxygen to formoxide.

[0008] In another embodiment of the device isolation process flow, theinsulating layer is formed by epitaxially growing Si with counterdopants over the rotor wafer substrate and heating the counter dopants.

[0009] The device isolation process flow inserts device isolation into aprocess flow of the ARS system so that the diodes may be electricallyinsulated from one another to improve signal to noise ratio. Inaddition, since most harsh processing are done prior to depositing thephase change layer, which stores data bits, process damage to the phasechange layer may be minimized.

DESCRIPTION OF THE DRAWINGS

[0010] The preferred embodiments of the device isolation process flowwill be described in detail with reference to the following figures, inwhich like numerals refer to like elements, and wherein:

[0011]FIG. 1 illustrates a prior art ARS system with non-isolateddevices;

[0012] FIGS. 2(a) and 2(b) illustrate an exemplary ARS system;

[0013]FIG. 3 illustrates the exemplary ARS system with isolated devices;

[0014] FIGS. 4(a)-4(f) illustrate an exemplary device isolation processflow for the ARS system;

[0015] FIGS. 5(a)-5(c) illustrate another method for device isolationfor the ARS system; and

[0016]FIG. 6 is a flow chart illustrating an exemplary device isolationprocess flow for the ARS system.

DETAILED DESCRIPTION

[0017] FIGS. 2(a) and 2(b) illustrate an exemplary ARS system 200. TheARS system 200 has high data storage capacity, up to 1000 Gb/in². TheARS system 200 is small, rugged, and portable. Additionally, the ARSsystem 200 has low power consumption, because there is typically nopower consumption when the ARS system 200 is not being asked to performan operation. Referring to FIG. 2(a), the ARS system 200 includes threebonded Si wafers, i.e., a tip wafer 210, also referred to as a firstwafer in this specification, a rotor wafer 220, also known as a moverwafer and referred to as a second wafer in this specification, and astator wafer 230. The rotor wafer 220, typically 100 microns thick, is ahighly doped Si substrate, which may be a n-type substrate or a p-typesubstrate. The wafers 210, 220, 230 are bonded together, as shown inFIG. 2(a), using wafer bonding techniques, which are well known in theart.

[0018] Each wafer-to-wafer bond requires internal cavity be sealed athigh vacuum using ultra-high vacuum (UHV) seals 202, which helps tomaintain the internal environment of the ARS chip. The wafer-to-waferbond also requires low resistance electrical contacts. For example, asshown in FIG. 2(a), conductive electrodes on a stator side of the rotorwafer 220 may be coupled with conductive electrodes on a rotor side ofthe stator wafer 230. Conductive electrodes on a media side of the rotorwafer 220 may be connected to complementary metal oxide semiconductor(CMOS) circuitry 232 located in the stator wafer 230. The tipelectronics 212, which are located in the stator wafer 230, controlsfield emitter tips 214 (shown in FIG. 2(b)) that are required tointerface with storage media 222 in the ARS system 200. The storagemedia 222, including medium recording cells 224 (shown in FIG. 2(b)),stores bits of data in the ARS system 200.

[0019] Read/write (R/W) electronics, which include the CMOS circuitry232, are also located in the stator wafer 230 beneath the conductiveelectrodes 234(b). The R/W electronics may control reading or writing ofdata bits in the storage media 222.

[0020] Through-wafer vias 226 enable electrical R/W signals (not shown)to pass from the CMOS circuitry 232 in the stator wafer 230 to theconductive electrodes on the media side of the rotor wafer 220, as wellas the tip electronics 212 in the tip wafer 210.

[0021]FIG. 2(b) illustrates the operation of the ARS system 200. Asingle field emitter tip 214 creates an electron beam 216 by drawingelectrons off a metal in the field emitter tip 214 with a high electricfield. The electron beam 216 is focused and used to write data bits ontothe storage media 212 by heating tiny data spots and altering the dataspots' physical state or phase. The electron beam 216 may also be usedto determine the data bit state (value) in the storage media 222. Anemitter tip array 218 is an array of field emitter tips 214, under whichthe storage media 222 is moved with nanometer precision. Suspensionsprings 240, shown in FIG. 2(b), may hold the rotor wafer 220 betweenthe field emitter tips 214 and the stator wafer 230 to allow the databits to be moved relative to the field emitter tips 214, thus allowingeach field emitter tip 214 to access multiple data bits.

[0022] For the ARS system 200 to operate, the rotor wafer 220 and thestator wafer 230 need to be processed, i.e., depositing conductiveelectrodes, for the nanometer precise position controls. Examples ofprocess flow for the ARS system 200 are described in United StatesPatent Applications of Lee, et al., entitled “Process Flow for ARS MoverUsing Selenidation Wafer Bonding After Processing A Media Side Of ARotor Wafer,” and “Process Flow for ARS Mover Using Selenidation WaferBonding Before Processing A Media Side Of A Rotor Wafer,” filed on thesame day herewith, which are incorporated herein by reference.

[0023] A device isolation process flow inserts device isolation into theprocess flow of the ARS system 200 so that diodes, i.e., smallelectronic devices embedded in a phase change layer 323 (describedlater) and a top active Si layer 330 (described later) and positioned onthe surface of the rotor wafer 220, may be electrically insulated fromone another. As a result, signal to noise ratio may be improved. Inaddition, since most harsh processing is done prior to depositing thephase change layer, which stores data bits, process damage to the phasechange layer may be minimized.

[0024]FIG. 3 illustrates an exemplary ARS system with isolated devices.A tip wafer 210, also referred to as an emitter wafer, may include aplurality of field emitter tips 214. The tip emitters 214 may bereplaced by flat emitters. An insulating layer 350, such as an embeddedoxide layer 350(a) (described later) or a counter doped semi-insulatingSi layer 350(b) (described later), may be formed beneath a top active Silayer 330 on the rotor wafer 220. A phase change layer 323, which mayserve as a storage media 222 to store data bits, may be deposited on topof the top active Si layer 330. The top active Si layer 330, along withthe phase change layer 323, may form a hetero junction p-n diode 370 forreading or writing data bits on the phase change layer 323 electrically.The hetero junction p-n diode 370 is typically formed when two differentmaterials with different conductivity types, active Si and phase changematerial in this case, make junction and cause electric current flow inone direction. A capping layer 360 may be coated over the phase changelayer 323 to protect the phase change layer 323 and to preventevaporation of material when heat is applied. The capping layer 360 mayalso modify the surface states of the phase change layer 323. The rotorwafer 220 may move in x and y direction to allow data bits to be writtento or read from the storage media 222.

[0025] The device isolation process may enable the multiple heterojunction p-n diodes 370 to become electrically isolated from each other,so that each isolated diode 370 may be coupled with each field emittertip 214. By moving the diodes 370 in the x and y direction, multipledata bits may be written in a single isolated diode 370, thus reducingchances of cross-talk between different diodes 370. With electronicsignal interferences reduced, the signal to noise ratio may be greatlyimproved for the ARS system 200. Signal to noise ratio refers to thesignal corresponding to reading the data bits.

[0026] FIGS. 4(a) to 4(f) illustrate an exemplary device isolationprocess flow for the ARS system 200. FIG. 4(a) illustrates ionimplantation of oxygen beneath the top active Si layer 330(a) on therotor wafer 220. After the implantation of oxygen, an insulating oxidelayer 350(a) maybe formed with heat treatment. The oxide layer 350(a)may electrically insulate the top active Si layer 330(a) and the rotorwafer 220, thereby preventing electron flowing between the top active Silayer 330(a) and the rotor wafer 220 body.

[0027] Referring to FIG. 4(b), the phase change layer 323(a) may beformed by depositing thin film of phase change material through thermalevaporation. The phase change materials are materials that canreversibly change phases from amorphous to crystalline. Amorphousmaterials typically have distorted atomic lattice and do not have a longrange order. On the other hand, crystalline materials have a periodicarray of atomic lattice with long range order. If crystalline materialsare ion implanted, i.e., implanting energetic ions into the crystallinematerials, the crystalline materials' lattice structure may be distortedby the implanted ions, and as a result, the crystalline materials maylose the long range order and become amorphous. The phase change layer323(a) may record the data bits as a form of amorphous spots withcrystalline background. Optionally, a protective capping layer 360 maybe coated over the phase change layer 323(a) to protect the phase changelayer surface and to prevent evaporation of material when heat isapplied.

[0028] Referring to FIG. 4(c), a masking layer 410, such as a SiO₂ layeror a photoresist (PR) layer, may be deposited over the phase changelayer 323(a). The masking layer 410 may be patterned using, for example,photolithography, and a predetermined portion of the masking layer 410may be etched.

[0029] Referring to FIG. 4(d), the exposed portion of the phase changelayer 323(a) corresponding to the removed portion of the masking layer410 may be etched using either dry or wet processes. Dry etching is adirectional and anisotrophic etching performed by plasma, i.e., mixtureof discharged gas and electrons and neutral atoms. Accordingly, dryetching may be widely used to transfer fine patterns. Wet etching isperformed by wet chemicals, such as acids and bases, and thus not verydirectional. Wet etching profile may be isotrophic, and therefore, wetetching is not suitable to transfer fine patterns as small assub-micron.

[0030]FIG. 4(e) illustrates the next step, etching the top active Silayer 330(a) until reaching the insulating oxide layer 350(a). Dryetching technique is typically used to define the top active Si layer330(a) due to dry etching's better pattern transfer ability. As aresult, the hetero junction p-n diodes 370, i.e., devices embedded inthe top active Si layer 330(a) and the phase change layer 323(a), maybecome electrically isolated from one another to enhance signal to noiseratio for the ARS system 200.

[0031] Referring to FIG. 4(f), the masking layer 410 may be removed.Optionally, a protective capping layer 360 may be coated over the phasechange layer 323(a) for protection.

[0032] FIGS. 5(a) to 5(c) illustrate another embodiment of the deviceisolation process flow for the ARS system 200. Instead of ionimplantation of oxygen through the rotor wafer 220, which is a highlydoped Si substrate, to form an electrically insulating layer, counterdopant may be ion implanted to form a semi-insulating Si layer 350(b).

[0033] First, crystalline Si may be grown on a Si substrate using anepitaxial technique. The Types, i.e., n-type or p-type, of the Si may becontrolled by adding dopant materials during the growth. Thesemi-insulating Si layer 350(b) may be formed between the rotor wafer220 and the top active Si layer 330(b) with an oppositely dopedepitaxial Si layer. This technique, which forms a reversed p-n junctiondiode, is referred to as “junction isolation.”

[0034] Because epitaxial Si may be grown, for example, at 600▾C. to650▾C., with a growth rate of, for example, 0.5 μm per minute, thermalbudget of epitaxial growth step is not fatal to heat sensitive CMOScircuitry in the stator wafer 230. In addition, the doping concentrationof the top active Si layer 330(b) may be independently optimized to therotor wafer 220 for best device performance.

[0035] Referring to FIG. 5(a), a p-type doped Si may be eqitaxiallygrown on an oppositely doped, i.e., n-type, Si rotor wafer 220substrate. Activating the p-type Si dopant with heat treatment may forma p-type semi-insulating Si layer 350(b). Alternatively, a n-type dopedSi may be epitaxially grown on a p-type Si rotor wafer 220 substrate toform a n-type semi-insulating Si layer.

[0036] Next, as shown in FIG. 5(b), a n-type doped Si may be epitaxiallygrown on top of the p-type dopant. A n-type top active Si layer 330(b)may be formed by activating the n-type Si dopant with heat treatment.Alternatively, a p-type doped Si may be grown on the n-type Si dopant toform a p-type top active Si layer.

[0037] Referring to FIG. 5(c), a p-type phase change layer 323(b) may beformed over the n-type top active Si layer 330(b) by depositing phasechange materials. Alternatively, a n-type phase change layer may beformed over the p-type top active Si layer. Optionally, a protectivecapping layer 360 may be deposited over the phase change layer 323(b).

[0038] Similar to FIGS. 4(c) to 4(f) (not shown in FIG. 5), the maskinglayer 410, such as a hard masking SiO₂ layer or a soft maskingphotoresist (PR) layer, may be deposited over the phase change layer323(b). The masking layer 410 may be patterned using, for example,photolighography, and a predetermined portion of the masking layer 410may be etched. Then, the exposed potion of the phase change layer323(b), corresponding to the removed portion of the masking layer 410,may be etched using either dry or wet processes.

[0039] Next, the top active Si layer 330(b) may be etched until reachingthe semi-insulating Si layer 350(b). As a result, the hetero junctionp-n diodes 370, i.e., devices embedded in the top active Si layer 330(b)and the phase change layer 323(b), may become electrically isolated fromone another to enhance signal to noise ratio for the ARS system 200.Finally, the masking layer 410 may be removed and the protective cappinglayer 360 may optionally be coated over the phase change layer 323(b)and the top active Si layer 330(b) for protection.

[0040]FIG. 6 is a flow chart illustrating the device isolation processflow for the ARS system 100. Step 610 involves ion implantation ofoxygen or counter dopant beneath the top active Si layer 330 on therotor wafer substrate 220, followed by heat treatment to form aninsulating layer 350 (step 612). Next, a phase change layer 323 may beformed by depositing phase change material over the top active Si layer330 (step 614). Optionally, a protective capping layer 360 may be coatedover the phase change layer 323 for protection.

[0041] Next, a masking layer 410, such as hard masking SiO₂ layer orsoft masking photoresist (PR) layer, may be deposited over the phasechange layer 323 (step 616). The masking layer 410 may be patternedusing photolighography (step 618) and a predetermined portion of themasking layer 410 may be etched (step 620). The exposed portion of thephase change layer 323 corresponding to the etched portion of themasking layer 410 may then be etched using either dry or wet processes(step 622). In step 624, the top active Si layer 330 may be etched untilreaching the insulating layer 350. Finally, the masking layer 410 may beremoved (step 626) and optionally, a protective capping layer 360 may bedeposited over the phase change layer 323 for protection (step 628).

[0042] While the device isolation process flow has been described inconnection with an exemplary embodiment, it will be understood that manymodifications in light of these teachings will be readily apparent tothose skilled in the art, and this application is intended to cover anyvariations thereof.

What is claimed is:
 1. A method for device isolation for an atomicresolution storage (ARS) system, comprising: forming an insulating layerbetween a wafer substrate and a top active silicon (Si) layer; forming aphase change layer over the top active Si layer; depositing a maskinglayer over the phase change layer, wherein the masking layer ispatterned and selectively etched; and etching the top active Si layerusing the masking layer as a mask until reaching the insulating layer,whereby devices embedded in the top active Si layer become electricallyisolated from one another.
 2. The method of claim 1, further comprisingdepositing a protective capping layer over the phase change layer. 3.The method of claim 1, further comprising removing the masking layer. 4.The method of claim 1, wherein the forming the insulating layer stepcomprises: ion implanting oxygen beneath the top active Si layer on thewafer substrate; and heating the oxygen to form oxide.
 5. The method ofclaim 1, wherein the forming the insulating layer step comprises:epitaxially growing Si with counter dopants over the wafer substrate;and heating the counter dopants.
 6. The method of claim 1, wherein thedepositing step includes patterning the masking layer usingphotolithography.
 7. An apparatus with isolated devices for an atomicresolution storage (ARS) system, comprising: a first wafer, wherein thefirst wafer includes field emitters that create electron beams bydrawing electrons off a metal in the field emitters, and wherein theelectron beams are used to write data bits onto storage media; and asecond wafer, wherein the second wafer is a highly doped silicon (Si)substrate, the second wafer comprises: devices embedded in a top activeSi layer, wherein the devices are isolated from one another, and eachdevice is coupled with each field emitter in the second wafer; and aninsulating layer positioned between the second wafer substrate and thetop active Si layer, wherein the devices are isolated by etching of thetop active Si layer until reaching the insulating layer in the secondwafer.
 8. The apparatus of claim 7, further comprising a phase changelayer positioned above the top active Si layer.
 9. The apparatus ofclaim 8, further comprising a protective capping layer over the phasechange layer.
 10. The apparatus of claim 7, wherein the field emittersare field emitter tips.
 11. The apparatus of claim 7, wherein the fieldemitters are flat emitters.
 12. The apparatus of claim 7, wherein theinsulating layer is formed by heating oxygen that is ion implantedbeneath the top active Si layer on the second wafer.
 13. The apparatusof claim 7, wherein the insulating layer is formed by heating counterdopants that are epitaxially grown over the second wafer.
 14. Theapparatus of claim 7, wherein the second wafer is a rotor wafer.
 15. Amethod for device isolation for an atomic resolution storage (ARS)system, comprising: forming an insulating layer between a wafersubstrate and a top active silicon (Si) layer; forming a phase changelayer over the top active Si layer; depositing a masking layer over thephase change layer; patterning the masking layer; selectively etchingthe masking layer; and etching the top active Si layer using the maskinglayer as a mask until reaching the insulating layer, whereby devicesembedded in the top active Si layer become electrically isolated fromone another.
 16. The method of claim 15, further comprising depositing aprotective capping layer over the phase change layer.
 17. The method ofclaim 15, further comprising removing the masking layer.
 18. The methodof claim 15, wherein the forming the insulating layer step comprises:ion implanting oxygen beneath the top active Si layer on the wafersubstrate; and heating the oxygen to form oxide.
 19. The method of claim15, wherein the forming the insulating layer step comprises: epitaxiallygrowing Si with counter dopants over the wafer substrate; and heatingthe counter dopants.
 20. The method of claim 15, wherein the patterningstep includes patterning the masking layer using photolithography.